july 1997 f dc 6 304p digital fet, dual p-channel general description features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter f dc 6 304p units v dss drain-source voltage -25 v v gss gate-source voltage -8 v i d drain current - continuous -0.46 a - pulsed -1 p d maximum power dissipation (note 1a) 0.9 w (note 1b) 0.7 t j ,t stg operating and storage temperature range -55 to 150 c esd electrostatic discharge rating mil-std-883d human body model (100pf / 1500 ohm) 6 .0 kv thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 140 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w fdc6304p rev.d -25 v, -0.46 a continuous, -1.0 a peak. r ds(on) = 1.5 w @ v gs = - 2.7 v r ds(on) = 1.1 w @ v gs = -4.5 v. very low level gate drive requirements allowing direct operation in 3v circuits. v gs(th) < 1.5 v. gate-source zener for esd ruggedness . >6 kv human body model . the se p -c hannel enhancement mode field effect transistor are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is tailored to minimize on-state resistance at low gate drive conditions. this device is designed especially for application in battery power applications such as notebook computers and cellular phones . this device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. mark: .304 sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 5 6 3 2 1 4 ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 a -25 v d bv dss / d t j breakdown voltage temp. coefficient i d = -250 a , referenced to 25 o c -22 mv / o c i dss zero gate voltage drain current v ds = -20 v, v gs = 0 v -1 a t j = 5 5c -10 a i gss gate - body leakage current v gs = -8 v, v ds = 0 v -100 na on characteristics (note 2 ) d v gs(th) / d t j gate threshold voltage temp. coefficient i d = -250 a , referenced to 25 o c 2.1 mv / o c v gs (th) gate threshold voltage v ds = v gs , i d = -250 a -0.65 -0.86 -1.5 v r ds(on) static drain-source on-resistance v gs = -2.7 v, i d = -0.25 a 1.22 1.5 w v gs = -4.5 v, i d = -0. 5 a 0.87 1.1 t j =12 5c 1.21 2 i d(on) on-state drain current v gs = -2.7 v, v ds = -5 v -0.5 a v gs = -4.5 v, v ds = -5 v -1 g fs forward transconductance v ds = -5 v, i d = -0.5 a 0.8 s dynamic characteristics c iss input capacitance v ds = -10 v, v gs = 0 v, f = 1.0 mhz 62 pf c oss output capacitance 35 pf c rss reverse transfer capacitance 9.5 pf switching ch aracteristics (note 2) t d(on ) turn - on delay time v dd = -6 v, i d = -0.5 a, v gs = -4.5 v, r gen = 50 w 7 20 ns t r turn - on rise time 8 20 ns t d(off) turn - off delay time 55 110 ns t f turn - off fall time 35 70 ns q g total gate charge v ds = -5 v, i d = - 0.25 a, v gs = -4.5 v 1.1 1.5 nc q gs gate-source charge 0.32 nc q gd gate-drain charge 0.28 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -0.5 a v sd drain-source diode forward voltage v gs = 0 v, i s = -0 .5 a (note 2 ) -0.88 -1.2 v notes: 1. r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdc6304p rev.d b. 180 o c/w on a 0.005 in 2 of pad of 2oz copper. a . 140 o c/w on a 0.125 in 2 pad of 2oz copper.
fdc6304p rev.d -5 -4 -3 -2 -1 0 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 v , drain-source voltage (v) i , drain-source current (a) v = -4.5v gs ds d -2.7 -2.5 -2.0 -3.0 -1.5 -3.5 0 0.25 0.5 0.75 1 0.5 1 1.5 2 2.5 -i , drain current (a) drain-source on-resistance v = -2.0 v gs d r , normalized ds(on) -3.5 -4.5 -2.7 -2.5 -3.0 typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . -3 -2.5 -2 -1.5 -1 -0.5 -1 -0.75 -0.5 -0.25 0 v , gate to source voltage (v) i , drain current (a) v = -5v ds gs d t = -55c j 125c 25c figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.01 0.1 0.5 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 6 . body diode forward voltage varia tion with source current and temperature. figure 4 . on resistance variation with gate-to - source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = -2.7v gs i = -0.25a d -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 0 1 2 3 4 5 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) 125c 25c i = -0.5a d
fdc6304p rev.d figure 10 . single pulse maximum power dissipation. 0.1 0.3 0.5 1 5 10 15 25 5 10 20 50 100 150 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical and thermal characteristics 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 q , gate charge (nc) -v , gate-source voltage (v) g gs i = -0.25a d 15v v = 5v ds 10v 0.1 0.2 0.5 1 2 5 10 20 40 0.01 0.03 0.1 0.3 1 2 - v , drain-source voltage (v) -i , drain current (a) rds(on) limit d a dc ds 1s 100ms 10ms 1ms v = -4.5v single pulse r = see note 1a t = 25c q ja gs a 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =see note 1a t = 25c q ja a 0.0001 0.001 0.01 0.1 1 10 100 300 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 r(t), normalized effective duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1b q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 11 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1b .transient thermal response will change depending on the circuit board design.
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